This invention relates generally to processing within a computing environment, and more particularly to reducing serialization of system requests.
The processing of a request by one processor of a computing environment may affect one or more other processors of the environment. For example, in a Symmetric Multiprocessing System (SMP) based on the IBM z/Architecture, there are certain broadcast purge operations such as Set Storage Key (SSKE), Invalidate Page Table Entry (IPTE), Invalidate DAT Table Entry (IDTE) and Compare and Swap and Purge (CSP and CSPG) which require all the processors in the system to quiesce in order to observe the system update(s) consistently. Other computer architectures also provide a similar mechanism.
One common implementation for the quiesce purge operation includes the following: 1) all the processors are quiesced (i.e., most normal processing operations are suspended, including accessing the TLB and ALB); 2) any buffered entries in the Translation Look-aside Buffers (TLBs) and/or in the Access-Register-Translation Look-aside Buffer (ALB) which are dependent on the resources being updated are invalidated; 3) the common resource (translation table entry in storage for IPTE, IDTE, CSP or CSPG or a storage key for SSKE) is updated, and 4) finally, the quiesce is released and the processors continue their normal activity. Obviously, this implementation could have a major performance impact, especially for large SMP configurations, since all processors must be quiesced for the duration of the operation. In particular, it is common that one processor is executing a long running instruction that is not interruptible, so that the one processor can not reach the quiesced state for some time. Thus, all other processors are required to wait for this last processor to reach the quiesced state before the steps described above can be completed.
Some strides have been made in the above processing to enhance performance by attempting to quiesce the processors for a shorter period of time. For example, in some implementations when a processor receives a request, it immediately quiesces and then purges the appropriate entries in its own TLB and/or ALB. After the purge is complete, this processor is allowed to continue processing subject to various restrictions. One of these restrictions includes that the processor is not permitted to perform address translation or fetch a storage key but instead must stall until the quiesce is released. Only after the quiesce is released, indicating that the system resources have been updated, are all restrictions removed from the processors.
Further strides to enhance performance are directed to reducing the restriction applied to address translation and key accesses during the quiesce window. For example, after purging its own TLB and/or ALB the purging processor is only restricted, using the page index (PX), segment index (SX) and/or absolute address of the translation, to perform an address translation or key access which potentially uses the system resources being updated by the quiesce operation. That restriction is referred to as the block-translation restriction.
Other performance enhancements have been directed to reducing the number of processors which need to honor the quiesce request. Since 1) the interruption of processors to honor the quiesce request is needed to prevent inconsistent values for translation tables or storage keys from being observed in the middle of an instruction or function and 2) when the active zone on the receiving processor is different from the zone which initiated the quiesce operation, the storage accesses being made by the receiving processor do not use the system resources that are being updated by the initiating zone, there is no need for processors running in a zone different than the quiesce-initiator's zone to be interrupted. This decreases the number of processors that need to be interrupted for a particular quiesce request and, in turn, also decreases the overall time needed to handle the quiesce request since the initiator needs to wait for fewer processors to respond to the interruption request.
Thus, although attempts have been made to reduce the amount of time processors are quiesced (e.g., for system resource updates), enhancements are still needed. For example, although fewer processors are required to honor the quiesce interruption and those processors that do honor the request are released early to do other work, only one quiesce request is allowed in the system at any given time.